The present invention relates to a Read Only Memory (ROM), and more particularly, to a ROM that operates at low power.
In general, the ROM stores data permanently once programmed. The ROM is classified into two types, a ROM having a NOR core cell or a ROM having a NAND core cell. The NAND core cell is advantageous in storage of a large capacity of data and the NOR core cell is advantageous in fast access of data.
The components that require the highest amount of power in the ROM are the bit lines. Each bit line is coupled to a capacitor. Accordingly, charging and discharging the capacitors are repeated in each bit line. Current ROMs include many junction capacitors within a chip, which occupy a large area. More particularly, when the ROM operates at low power of about 1.8 V, there are many difficulties in sensing data accurately and transferring the sensed data to the chip.
FIG. 1 is a schematic block diagram of a conventional low power ROM. A ROM 10 includes a ROM core unit 20, a word line decoder 30, a column decoder 40, and capacitor control units C1 to Ci. The ROM core unit 20 includes ROM cores (not shown) and retains stored data. The word line decoder 30 is coupled to the ROM core unit 20 through word lines WL1 to WLk and transfers a word line select signal. The column decoder 40 is coupled to the ROM core unit 20 through bit lines and transfers a bit line select signal. The capacitor control units C1 to Ci are grouped with a plurality of ROM cores (not shown) and serve to read and output data.
FIG. 2 is a detailed circuit diagram of the low power ROM shown in FIG. 1. The ROM core unit 20 includes a plurality of ROM cores. The plurality of ROM cores include NMOS transistors A1 to Ak, B1 to Bk, . . . , n1 to nk, which are coupled to the bit lines BL1 to BLn and the word lines WL1 to WLk, respectively. The ROM core unit 20 disconnects or connects nodes coupled between the NMOS transistors and the bit lines, so that data are stored.
It is assumed in FIG. 2 that all the nodes are coupled. Each of the capacitor control units C1 to Ci includes transistors P1 and N1 to N6, capacitors CCS, CH, and CI, and a comparator BF. Each of the capacitor control units C1 to Ci is coupled to the plurality of ROM cores coupled to the plurality of bit lines, thus forming groups CG1 to CGi. The capacitor CCS is used to distribute charge to all groups CG1 to CGi and the capacitors CH, CI are used for sensing.
In this case, when the number of groups is plural, the number of capacitors must also be plural and the connection lines corresponding to the groups are also required. The plurality of groups, capacitors and connection lines occupies a large area. Furthermore, since power capable of driving all the plurality of capacitors is required, power consumption is increased accordingly.